US 11,734,193 B2
Exclusion regions for host-side memory address translation
Christian M. Gyllenskog, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 19, 2021, as Appl. No. 17/531,581.
Claims priority of provisional application 63/125,303, filed on Dec. 14, 2020.
Prior Publication US 2022/0188246 A1, Jun. 16, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1045 (2013.01) [G06F 12/0246 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller of a host system configured to couple with a memory system, wherein the controller is configured to cause the apparatus to:
identify, at the host system, one or more regions of logical addresses of the memory system associated with exclusion from operating according to logical to physical address mapping by the host system for access commands; and
signal, to the memory system, an indication to inhibit communication of tables for logical to physical address mapping by the host system for the one or more regions.