US 11,734,191 B2
User process identifier based address translation
Prateek Sharma, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,581.
Application 17/711,581 is a continuation of application No. 16/990,941, filed on Aug. 11, 2020, granted, now 11,321,238.
Prior Publication US 2022/0222182 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 9/54 (2006.01); G06F 9/455 (2018.01)
CPC G06F 12/1009 (2013.01) [G06F 9/45558 (2013.01); G06F 9/546 (2013.01); G06F 12/1063 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/152 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processing device of a host, coupled with a memory device of a memory sub-system, to:
receive a first address from the memory sub-system for translation;
map the first address to a second address utilizing host memory; and
provide the second address to the memory sub-system to access the memory device utilizing the second address.