US 11,734,189 B2
Caching of logical-to-physical mapping information in a memory sub-system
Sanjay Subbarao, Irvine, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 16, 2021, as Appl. No. 17/203,017.
Prior Publication US 2022/0300432 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 12/1009 (2016.01); G06F 12/0875 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0875 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:
receiving a request specifying a logical address associated with a host-initiated operation directed at a first portion of the memory device; and
providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;
the secondary FTL configured to perform operations comprising:
accessing, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
identifying an entry in the L2P table that corresponds to the logical address;
determining the entry in the L2P table points to an entry in a read cache table;
calculating a chunk address corresponding to a chunk from among multiple chunks of a read cache based on a combination of an entry number of the entry in the read cache table, a unit size of chunks in the read cache, and the logical address associated with the host-initiated operation directed at the first portion of the memory device, the chunk in the read cache storing information that specifies a physical address within the first portion of the memory device that corresponds to the logical address specified by the request;
identifying, based on the chunk of the read cache corresponding to the chunk address, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device; and
providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.