CPC G06F 12/0891 (2013.01) [G06F 12/0238 (2013.01); G06F 12/0848 (2013.01); G06F 12/1458 (2013.01); G06F 2212/1021 (2013.01)] | 20 Claims |
1. A system comprising:
a line cache;
a memory device; and
a processing device operatively coupled to the line cache and the memory device, the processing device comprising a buffer manager and a high-speed mode driver, the processing device to perform operations comprising:
detecting that one or more received events are located in an events list, wherein events stored in the events list are associated with a set of functions that are known to cause a clock domain crossing between the buffer manager and a host system;
enabling access to the line cache;
determining one or more functions of the set of functions that correspond to the one or more received events; and
running, using the high-speed mode driver, in a high-speed mode to execute the one or more functions out of the line cache on behalf of the host system.
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