US 11,734,184 B2
Effective avoidance of line cache misses
Meng Wei, Shanghai (CN); Shi Bo Zhang, Shanghai (CN); and Tao Xiong, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 4, 2022, as Appl. No. 17/687,103.
Application 17/687,103 is a continuation of application No. 15/733,358, granted, now 11,288,198, previously published as PCT/CN2019/127367, filed on Dec. 23, 2019.
Prior Publication US 2022/0261353 A1, Aug. 18, 2022
Int. Cl. G06F 12/0891 (2016.01); G06F 12/02 (2006.01); G06F 12/0846 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0238 (2013.01); G06F 12/0848 (2013.01); G06F 12/1458 (2013.01); G06F 2212/1021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a line cache;
a memory device; and
a processing device operatively coupled to the line cache and the memory device, the processing device comprising a buffer manager and a high-speed mode driver, the processing device to perform operations comprising:
detecting that one or more received events are located in an events list, wherein events stored in the events list are associated with a set of functions that are known to cause a clock domain crossing between the buffer manager and a host system;
enabling access to the line cache;
determining one or more functions of the set of functions that correspond to the one or more received events; and
running, using the high-speed mode driver, in a high-speed mode to execute the one or more functions out of the line cache on behalf of the host system.