CPC G06F 12/0882 (2013.01) [G06F 2212/1024 (2013.01); G06F 2212/2022 (2013.01)] | 19 Claims |
1. A method for operating a memory device having a memory array, a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache, the method comprising:
executing a continuous read operation to sequentially load data segments to the data register and to move the data segments from the data register to the cache, in response to a read command;
executing a cache read operation to move data from the cache to the input/output interface in response to a current cache read command and stalling movement of data from the cache to the input/output interface until a next cache read command in a sequence of cache read commands, wherein the data moved to the input/output interface in the cache read operation has a length determined by a number of clock cycles of a clock signal, and the stalling includes stopping the clock signal; and
terminating the continuous read operation.
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