US 11,734,181 B2
Continuous read with multiple read commands
Shuo-Nan Hung, Hsinchu (TW); and Chun-Lien Su, Taichung (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Jan. 19, 2022, as Appl. No. 17/579,428.
Application 17/579,428 is a continuation of application No. 17/061,451, filed on Oct. 1, 2020, granted, now 11,249,913.
Claims priority of provisional application 62/985,898, filed on Mar. 6, 2020.
Prior Publication US 2022/0138109 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0882 (2016.01)
CPC G06F 12/0882 (2013.01) [G06F 2212/1024 (2013.01); G06F 2212/2022 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for operating a memory device having a memory array, a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache, the method comprising:
executing a continuous read operation to sequentially load data segments to the data register and to move the data segments from the data register to the cache, in response to a read command;
executing a cache read operation to move data from the cache to the input/output interface in response to a current cache read command and stalling movement of data from the cache to the input/output interface until a next cache read command in a sequence of cache read commands, wherein the data moved to the input/output interface in the cache read operation has a length determined by a number of clock cycles of a clock signal, and the stalling includes stopping the clock signal; and
terminating the continuous read operation.