US 11,734,170 B2
Host-resident translation layer validity check
David Aaron Palmer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 23, 2022, as Appl. No. 17/679,018.
Application 17/679,018 is a continuation of application No. 16/054,072, filed on Aug. 3, 2018, granted, now 11,263,124.
Prior Publication US 2022/0179783 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 12/0873 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0871 (2013.01); G06F 12/0873 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/305 (2013.01); G06F 2212/608 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a memory request from a host at a memory system, the memory request including a logical block address (LBA) and a first physical address;
identifying a second physical address from the LBA by referencing a portion of a logical-to-physical mapping table;
determining that the second physical address does not match the first physical address received in the memory request;
responsive to determining that the second physical address does not match the first physical address received in the memory request:
executing a memory operation associated with the memory request using the second physical address;
generating a response to the memory request;
identifying a counter associated with a range of LBAs inclusive of the LBA;
incrementing the counter associated with the range of LBAs;
determining that the counter exceeds a prespecified threshold; and
responsive to determining that the counter exceeds the prespecified threshold, sending to the host, physical address mappings for the range of LBAs, including the second physical address.