CPC G06F 11/263 (2013.01) [G06F 1/10 (2013.01); G06F 11/2273 (2013.01); G06F 11/267 (2013.01); G11C 29/1201 (2013.01); G11C 29/32 (2013.01); G11C 29/48 (2013.01)] | 20 Claims |
1. A method for operating a memory storage device, the memory storage device including a memory array and circuitry under test, the method comprising:
providing, by first latching circuitry within the memory storage device, an input sequence of data in accordance with a memory clocking signal;
operating on, by the circuitry under test, the input sequence of data to provide a first sequence of output data;
providing, by second latching circuitry within the memory storage device, the input sequence of data as a second sequence of output data in accordance with the memory clocking signal; and
selecting, by multiplexing circuitry within the memory storage device, the first sequence of output data or the second sequence of output data as an output sequence of data.
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