US 11,734,015 B2
Cache systems and circuits for syncing caches or cache sets
Steven Jeffrey Wallach, Dallas, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 13, 2022, as Appl. No. 17/838,606.
Application 17/838,606 is a continuation of application No. 17/163,163, filed on Jan. 29, 2021, granted, now 11,360,777.
Application 17/163,163 is a continuation of application No. 16/528,479, filed on Jul. 31, 2019, granted, now 10,915,326, issued on Feb. 9, 2021.
Prior Publication US 2022/0308886 A1, Sep. 29, 2022
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 12/0842 (2016.01); G06F 13/16 (2006.01)
CPC G06F 9/3842 (2013.01) [G06F 9/30098 (2013.01); G06F 12/0842 (2013.01); G06F 13/1684 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first cache and a second cache; and
a logic circuit configured to:
control the first cache according to a first execution type of non-speculative execution instructions by a processor; and
control the second cache according to a second execution type of speculative execution of instructions by the processor, wherein after a condition associated with the second execution type is confirmed, the logic circuit is further configured to switch the control of the second cache to the first execution type.