US 11,734,005 B2
Processor with split read
Zachy Haramaty, Hemed (IL); Yaniv Strassberg, Yokneam (IL); Itsik Levi, Shapir (IL); and Alon Singer, Tel Aviv (IL)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Jul. 4, 2021, as Appl. No. 17/367,367.
Prior Publication US 2023/0004392 A1, Jan. 5, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 12/02 (2006.01)
CPC G06F 9/30101 (2013.01) [G06F 12/023 (2013.01); G06F 2212/251 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor, to issue a set of one or more split read requests for loading one or more data values to one or more respective local registers of the processor; and
split-read control circuitry (SRCC), to receive the set of one or more read requests, to acknowledge a given read request in the set to the processor regardless of whether the given read request has been completed, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers.