US 11,733,929 B2
Memory system with dynamic calibration using a variable adjustment mechanism
Michael Sheperek, Longmont, CO (US); Larry J. Koudele, Erie, CO (US); and Steve Kientz, Westminster, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/819,857.
Application 17/819,857 is a continuation of application No. 16/850,224, filed on Apr. 16, 2020, granted, now 11,416,173.
Application 16/850,224 is a continuation of application No. 15/981,796, filed on May 16, 2018, granted, now 10,664,194, issued on May 26, 2020.
Prior Publication US 2022/0391143 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device comprising a plurality of memory cells; and
a processing device coupled to the memory device, the processing device configured to:
iteratively update a read level according to a first step size;
detect a change in update pattern during the iterative update of the read level according to the first step size; and
iteratively update the read level according to a second step size based on the detected change.