US 11,733,928 B2
Read sample offset bit determination in a memory sub-system
Michael Sheperek, Longmont, CO (US); and Bruce A. Liikanen, Berthoud, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 28, 2022, as Appl. No. 17/706,157.
Application 17/706,157 is a continuation of application No. 16/507,844, filed on Jul. 10, 2019, granted, now 11,288,009.
Prior Publication US 2022/0214837 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/12 (2006.01); G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01); G11C 16/3418 (2013.01); G11C 16/3422 (2013.01); G11C 2216/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
generating a first set of read data associated with a memory component, the first set of read data comprising a first sequence of bit values;
generating a second set of read data associated with the memory component, the second set of read data comprising a second sequence of bit values;
generating a third set of read data associated with the memory component, the third set of read data comprising a third sequence of bit values;
performing, by a processing device, a most probable bit operation to compare the first sequence of bit values, the second sequence of bit values, and the third sequence of bit values to generate a most probable bit sequence corresponding to the read data associated with the memory component; and
causing the most probable bit sequence to be stored.