US 11,733,925 B2
Enabling multiple data capacity modes at a memory sub-system
Fangfang Zhu, San Jose, CA (US); Chih-Kuo Kao, Fremont, CA (US); Jiangli Zhu, San Jose, CA (US); and Ying Yu Tai, Mountain View, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 30, 2021, as Appl. No. 17/461,759.
Prior Publication US 2023/0062189 A1, Mar. 2, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A system comprising:
a plurality of memory devices; and
a processing device coupled to each of the plurality of memory devices, the processing device to perform operations comprising:
receiving a request to access a data item associated with a portion of a memory device of the plurality of memory devices via a logical data channel of a plurality of logical data channels;
determining whether the system is operating in a full capacity mode or a reduced capacity mode, wherein the full capacity mode corresponds to accessing data residing at the plurality of memory devices via a number of data channels that correspond to a number of the plurality of logical data channels and the reduced capacity mode corresponds to accessing the data via a number of data channels that is less than the number of plurality of logical data channels;
responsive to determining that the system is operating in the reduced capacity mode, identifying at least one of an additional portion of the memory device or a portion of an additional memory device of the plurality of memory devices that corresponds to a data channel that is associated with the logical data channel; and
executing a memory access operation to access the data item at memory cells of the at least one of the additional portion of the memory device or the portion of the additional memory device.