CPC G06F 3/0658 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G11C 13/004 (2013.01); G11C 2213/71 (2013.01)] | 20 Claims |
1. A memory system, comprising:
a memory controller,
a data bus electrically coupled to the memory controller; and
one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices is located at a different respective distance from the memory controller, and wherein each of the one or more memory devices comprises an adaptive read output timing circuit configured to adaptively adjust a read output timing using a read training setting stored on the respective one or more memory devices during a read training, wherein the read training setting is based at least in part on the respective distance of each of the one or more memory devices from the memory controller.
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