US 11,733,915 B2
Systems and methods for adaptive read training of three dimensional memory
Yang Lu, Boise, ID (US); and Christopher Heaton Stoddard, Caldwell, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 19, 2022, as Appl. No. 17/749,000.
Application 17/749,000 is a continuation of application No. 17/006,580, filed on Aug. 28, 2020, granted, now 11,340,831.
Prior Publication US 2022/0276805 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 3/0658 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G11C 13/004 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller,
a data bus electrically coupled to the memory controller; and
one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices is located at a different respective distance from the memory controller, and wherein each of the one or more memory devices comprises an adaptive read output timing circuit configured to adaptively adjust a read output timing using a read training setting stored on the respective one or more memory devices during a read training, wherein the read training setting is based at least in part on the respective distance of each of the one or more memory devices from the memory controller.