US 11,733,892 B2
Partial superblock memory management
Xiangang Luo, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Huachen Li, San Jose, CA (US); Giuseppe D'eliseo, Caserta (IT); and Jianmin Huang, San Carlos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 29, 2021, as Appl. No. 17/362,542.
Prior Publication US 2022/0413699 A1, Dec. 29, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying bad blocks in respective planes of a block of non-volatile memory cells of a plurality of blocks of NAND memory cells in a non-volatile memory device;
determining that a plane of the respective planes includes at least one good block in at least one different block of non-volatile memory cells of the plurality of blocks of non-volatile memory cells; and
performing an operation to reallocate the at least one good block in the plane to at least one bad block of the bad blocks in the plane to form a plurality of partial superblocks of non-volatile memory cells each of the partial superblocks having a quantity of bad blocks that satisfies a bad block threshold, wherein the bad block threshold is determined based on a permissible amount of latency that is based on a quantity of permissible bad blocks, in a partial superblock, divided by a quantity of the respective planes of the partial superblock.