US 11,733,887 B2
Write training in memory devices by adjusting delays based on data patterns
Luigi Pilolli, L'Aquila (IT); Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US); Guan Wang, San Jose, CA (US); and Qiang Tang, Cupertino, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 11, 2021, as Appl. No. 17/316,956.
Application 17/316,956 is a division of application No. 16/171,442, filed on Oct. 26, 2018.
Prior Publication US 2021/0263660 A1, Aug. 26, 2021
Int. Cl. G06F 3/06 (2006.01); G11C 16/32 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/32 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of input/output (I/O) nodes to receive a plurality of periods of a predefined data pattern;
a circuit to adjust a delay for each I/O node as the predefined data pattern is received;
a latch to latch the data received on each I/O node in response to a data strobe signal;
a memory to store the latched data; and
control logic to:
sweep, via the circuit, the delay for each I/O node to adjust a signal edge for each I/O node as the predefined data pattern is received;
compare the stored latched data to an expected data pattern;
generate a table indicating which stored latched data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored latched data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node; and
adjust setup and hold time margins for each I/O node by setting, via the circuit, the delay for each I/O node based on the table indicating which stored latched data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node.