US 11,733,879 B2
Data processing system and method for reading instruction data of instruction from memory including a comparison stage for preventing execution of wrong instruction data
Oron Michael, San Jose, CA (US); and Katsutoshi Suito, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Oct. 14, 2022, as Appl. No. 17/965,796.
Application 17/965,796 is a continuation of application No. 17/111,527, filed on Dec. 4, 2020, granted, now 11,507,282.
Prior Publication US 2023/0035098 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system, comprising:
a memory, including a first region and a second region;
a read data check circuit, coupled to the second region of the memory to receive a dummy data, and comparing the dummy data to a hardwire data; and
a microprocessor, coupled to the memory and the read data check circuit, configured to access the memory using an instruction address to fetch instruction data, receive the instruction data from the first region and a comparison result from the read data check circuit in response to the instruction address, and determine whether to execute the instruction data corresponding to the instruction address according to the comparison result, wherein the hardwire data having a bit pattern represents a command to control the microprocessor.