CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
1. A data processing system, comprising:
a memory, including a first region and a second region;
a read data check circuit, coupled to the second region of the memory to receive a dummy data, and comparing the dummy data to a hardwire data; and
a microprocessor, coupled to the memory and the read data check circuit, configured to access the memory using an instruction address to fetch instruction data, receive the instruction data from the first region and a comparison result from the read data check circuit in response to the instruction address, and determine whether to execute the instruction data corresponding to the instruction address according to the comparison result, wherein the hardwire data having a bit pattern represents a command to control the microprocessor.
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