US 11,733,873 B2
Wear leveling in solid state drives
Zoltan Szubbocsev, Haimhausen (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 1, 2017, as Appl. No. 15/829,590.
Prior Publication US 2019/0171372 A1, Jun. 6, 2019
Int. Cl. G06F 3/06 (2006.01); G06F 12/10 (2016.01); G11C 11/00 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/16 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0649 (2013.01); G06F 3/0688 (2013.01); G06F 12/10 (2013.01); G11C 11/005 (2013.01); G11C 16/3486 (2013.01); G11C 16/3495 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/657 (2013.01); G11C 11/5635 (2013.01); G11C 16/16 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A solid state drive, comprising:
a host interface;
a controller;
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
firmware containing instructions configured to instruct the controller to:
generate an address map mapping logical addresses to physical addresses of the memory units of the different types;
adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
track numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.