US 11,733,763 B2
Intelligent low power modes for deep learning accelerator and random access memory
Poorna Kale, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 6, 2020, as Appl. No. 16/987,127.
Prior Publication US 2022/0043502 A1, Feb. 10, 2022
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G06F 1/3287 (2019.01); G06F 1/3228 (2019.01); G06F 17/16 (2006.01); G06N 3/08 (2023.01); G06F 9/50 (2006.01); G06F 9/30 (2018.01); G06N 3/063 (2023.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3228 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/3001 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A device, comprising:
random access memory having a plurality of memory groups, each of the memory groups configured with a plurality of power modes, the random access memory configured to store first data representative of parameters of an artificial neural network and store second data representative of instructions having matrix operands, the instructions executable to implement matrix computations of the artificial neural network using at least the first data representative of the parameters of the artificial neural network;
at least one processing unit coupled with the random access memory and configured to execute the instructions represented by the second data to generate an output of the artificial neural network by performing the matrix computations on the matrix operands of the second data using the parameters of the artificial neural network in the first data stored in the random access memory; and
a power manager configured to cause, during execution of the instructions represented by the second data, a first memory group in the random access memory to enter a first power mode at a first time instance and to enter a second power mode at a second time instance, wherein the first memory group and other memory groups of the plurality of memory groups are a same type of random access memory, wherein during the first power mode the first memory group is not being accessed, and further wherein during the second power mode the first memory group is being accessed.