US RE50,547 E1
Integrated circuit device including vertical memory device and method of manufacturing the same
Shin-Hwan Kang, Seoul (KR); Young-Hwan Son, Hwaseong-si (KR); Dong-seog Eun, Seongnam-si (KR); Chang-sup Lee, Hwaseong-si (KR); and Jae-hoon Jang, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 21, 2022, as Appl. No. 17/870,191.
Application 17/870,191 is a division of application No. 17/668,441, filed on Feb. 10, 2022, granted, now RE50225.
Application 15/946,432 is a division of application No. 15/345,763, filed on Nov. 8, 2016, granted, now 9,991,271, issued on Jun. 5, 2018.
Application 17/668,441 is a reissue of application No. 15/946,432, filed on Apr. 5, 2018, granted, now 10,886,289, issued on Jan. 5, 2021.
Application 17/870,191 is a reissue of application No. 15/946,432, filed on Apr. 5, 2018, granted, now 10,886,289, issued on Jan. 5, 2021.
Claims priority of application No. 10-2016-0071890 (KR), filed on Jun. 9, 2016.
Int. Cl. H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/50 (2023.02)] 20 Claims
OG exemplary drawing
 
[ 13. A device comprising:
a substrate including a cell array region and a contact region;
a lower dielectric layer on the substrate;
an alternating stack of insulating layers and conductive layers on the lower dielectric layer, the alternating stack including stepped surfaces on the contact region of the substrate;
a first insulating portion on the stepped surfaces of the alternating stack; and
a first vertical structure vertically extending through the alternating stack and the first insulating portion, and including a vertical channel pattern that extends through at least one of the conductive layers and a dielectric layer pattern that laterally surrounds the vertical channel pattern,
wherein one of the conductive layers laterally surrounds a portion of the dielectric layer pattern, and
the lower dielectric layer extends through at least a portion of a bottom surface of a bottommost one of the conductive layers.]