US 12,396,380 B1
Resistive random access memory structure and fabricating method of the same
Po-Kai Hsu, Tainan (TW); and Chung-Yi Chiu, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Apr. 13, 2023, as Appl. No. 18/134,048.
Application 18/134,048 is a continuation in part of application No. 17/541,226, filed on Dec. 2, 2021, granted, now 11,665,913.
Claims priority of application No. 202111287182.1 (CN), filed on Nov. 2, 2021.
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/8833 (2023.02) [H10B 63/30 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A resistive random access memory structure, comprising:
a substrate;
a transistor disposed on the substrate, wherein the transistor comprises a gate structure, a source and a drain;
an interlayer dielectric layer covering and contacting the transistor;
a drain contact plug disposed within the interlayer dielectric layer and contacting the drain,
and wherein an end of the drain contact plug protrudes from the interlayer dielectric layer;
a metal interlayer dielectric layer disposed on and contacting the interlayer dielectric layer;
a resistive random access memory (RRAM) disposed on the drain and within a first trench in the metal interlayer dielectric layer, wherein the RRAM comprises a bottom electrode, a metal oxide layer and a top electrode, the drain contact plug contacts the bottom electrode, the bottom electrode contacts the metal oxide layer and the top electrode contacts the metal oxide layer; and
a metal layer disposed within the first trench.