US 12,396,372 B2
Semiconductor device and manufacturing method of semiconductor device
Chien-Min Lee, Hsinchu (TW); Shy-Jay Lin, Jhudong Township (TW); Yen-Lin Huang, Hsinchu (TW); MingYuan Song, Hsinchu (TW); and Tung Ying Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 28, 2023, as Appl. No. 18/308,914.
Application 18/308,914 is a continuation of application No. 17/369,484, filed on Jul. 7, 2021, granted, now 11,706,999.
Claims priority of provisional application 63/136,737, filed on Jan. 13, 2021.
Prior Publication US 2023/0292631 A1, Sep. 14, 2023
Int. Cl. H10N 52/80 (2023.01); H10B 61/00 (2023.01); H10N 50/85 (2023.01); H10N 52/01 (2023.01)
CPC H10N 52/80 (2023.02) [H10B 61/22 (2023.02); H10N 50/85 (2023.02); H10N 52/01 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory cell comprising:
a composite spin Hall electrode over a first transistor and a second transistor, the first transistor being electrically connected to a first terminal of the composite spin Hall electrode, and the second transistor being electrically connected to a second terminal of the composite spin Hall electrode; and
a magnetic tunnel junction over the composite spin Hall electrode, wherein the composite spin Hall electrode comprises:
a first metal layer;
a spacer layer over the first metal layer, wherein the spacer layer comprises magnesium oxide; and
a second metal layer over the spacer layer; and
a first buffer layer between the magnetic tunnel junction and the composite spin Hall electrode.