US 12,396,371 B2
Three-state memory device
Mauricio Manfrini, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 5, 2024, as Appl. No. 18/764,426.
Application 18/764,426 is a division of application No. 17/412,509, filed on Aug. 26, 2021, granted, now 12,075,710.
Prior Publication US 2024/0365680 A1, Oct. 31, 2024
Int. Cl. H10N 50/80 (2023.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a bottom electrode arranged within a dielectric layer;
a memory element directly over the bottom electrode and arranged within the dielectric layer;
a top electrode directly over the memory element and arranged within the dielectric layer; and
a conductive via directly over the top electrode,
wherein a pair of lines that extend along opposing sidewalls of the top electrode are over, and intersect, an uppermost surface of the memory element, and wherein the pair of lines are under, and intersect, a lowermost surface of the conductive via.