US 12,396,370 B2
MRAM structure with high TMR and high PMA
Ming-Yen Chuang, Hsinchu (TW); and Wenchin Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,422.
Application 17/874,422 is a division of application No. 16/411,761, filed on May 14, 2019, granted, now 11,469,369.
Prior Publication US 2022/0367789 A1, Nov. 17, 2022
Int. Cl. H10N 50/80 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, comprising:
forming a memory cell stack over a substrate, wherein the memory cell stack comprises a tunnel barrier layer, a free layer over the tunnel barrier layer, a capping dielectric layer over the free layer, and a conductive capping layer on the capping dielectric layer, wherein the free layer comprises a first magnetic orientation or a second magnetic orientation; and
performing an etching process on the memory cell stack to define outer sidewalls of the free layer, outer sidewalls of the capping dielectric layer, and outer sidewalls of the conductive capping layer, wherein the etching process forms a conductive shunting structure along the outer sidewalls of the free layer, the outer sidewalls of the capping dielectric layer, and the outer sidewalls of the conductive capping layer, wherein a bottommost point of the conductive shunting structure in contact with the free layer is disposed above a bottom surface of the free layer.