US 12,396,330 B2
Display device
Yeonhwa Lee, Hwaseong-si (KR); Hye Jin Gwark, Suwon-si (KR); Arong Kim, Hwaseong-si (KR); Jaeik Kim, Seoul (KR); Jungsun Park, Yongin-si (KR); Heemin Park, Hwaseong-si (KR); Joongu Lee, Seoul (KR); Hyoung Sub Lee, Yongin-si (KR); and Kyu Hwan Hwang, Seongnam-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on May 2, 2022, as Appl. No. 17/734,380.
Claims priority of application No. 10-2021-0104124 (KR), filed on Aug. 6, 2021.
Prior Publication US 2023/0039703 A1, Feb. 9, 2023
Int. Cl. H10K 59/122 (2023.01); H10K 50/844 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 102/10 (2023.01)
CPC H10K 59/122 (2023.02) [H10K 50/844 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 2102/102 (2023.02); H10K 2102/103 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a base layer;
a circuit layer including a plurality of transistors spaced apart from each other and disposed on a top of the base layer, a plurality of insulating layers disposed on a top of the base layer, and a plurality of contact electrodes electrically connected to the plurality of transistors, respectively;
a first light emitting unit including a first lower electrode disposed on a top of the circuit layer, a first pixel defining layer disposed on a top of the first lower electrode, wherein a first pixel opening for exposing the first lower electrode is defined in the first pixel defining layer, a first light emitting layer disposed on a top of the first lower electrode, a first upper electrode disposed on a top of the first light emitting layer, and a first encapsulation layer disposed on a top of the first upper electrode;
a second light emitting unit including a second lower electrode disposed on a top of the first light emitting unit, a second pixel defining layer disposed on a top of the second lower electrode, wherein a second pixel opening for exposing the second lower electrode is defined in the second pixel defining layer, a second light emitting layer disposed on a top of the second lower electrode, a second upper electrode disposed on a top of the second light emitting layer, and a second encapsulation layer disposed on a top of the second upper electrode; and
a lower protrusion disposed between at least one of the transistors and the second lower electrode,
wherein at least one of the contact electrodes is disposed to extend to a top surface of the lower protrusion in the circuit layer while following a shape of the lower protrusion.