US 12,396,329 B2
Display apparatus
Youngwan Seo, Yongin-si (KR); Jisun Kim, Yongin-si (KR); Kyunghoe Lee, Yongin-si (KR); and Keunhee Choi, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Mar. 25, 2022, as Appl. No. 17/704,095.
Claims priority of application No. 10-2021-0039779 (KR), filed on Mar. 26, 2021.
Prior Publication US 2022/0310736 A1, Sep. 29, 2022
Int. Cl. H10K 59/121 (2023.01); H10K 59/12 (2023.01); H10K 59/123 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1216 (2023.02) [H10K 59/1213 (2023.02); H10K 59/131 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a substrate including a first area and a second area disposed adjacent to the first area;
a first pixel arranged in the first area;
a first pixel circuit arranged in the first area, electrically connected to the first pixel, and overlapping at least a portion of the first pixel; and
a second pixel arranged in the second area and electrically connected to the first pixel circuit,
wherein the first pixel circuit comprises a first storage capacitor and a second storage capacitor that are connected in parallel to each other between a driving voltage line and a gate electrode of a first thin-film transistor,
wherein the first storage capacitor comprises a first electrode and a second electrode disposed on the first electrode and at least partially overlapping with the first electrode,
wherein the second storage capacitor comprises the second electrode and a third electrode disposed on the second electrode and at least partially overlapping with the second electrode, and
wherein the first pixel circuit comprises:
the first thin-film transistor comprising the first gate electrode and a first semiconductor layer, the first gate electrode being arranged in a same layer as the first electrode and the first semiconductor layer being arranged below the first gate electrode; and
a second thin-film transistor comprising a second gate electrode and a second semiconductor layer, the second gate electrode being arranged in a same layer as the third electrode and the second semiconductor layer being arranged below the second gate electrode.