| CPC H10K 59/1213 (2023.02) [H10D 86/411 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01); H10D 86/60 (2025.01); H10K 59/131 (2023.02); H01L 2224/16225 (2013.01); H10D 30/6731 (2025.01); H10D 30/6745 (2025.01); H10D 30/6755 (2025.01); H10D 86/481 (2025.01); H10K 59/40 (2023.02)] | 4 Claims |

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1. An array substrate structure, comprising:
a substrate;
a first transistor disposed on the substrate, comprising a first semiconductor layer having a drain region;
a second transistor disposed on the substrate, comprising a gate electrode;
a second semiconductor layer disposed under the gate electrode;
an electrode directly connected to the second semiconductor layer; and
a light-emitting element electrically connected to the second semiconductor layer through the electrode;
wherein the drain region of the first semiconductor layer is electrically connected to the gate electrode of the second transistor;
wherein the gate electrode of the second transistor is a part of a storage capacitor.
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