US 12,396,314 B2
Method of patterning a semiconductor layer
Yi-Ming Chang, Hsinchu (TW)
Assigned to Raynergy Tek Incorporation, Hsinchu (TW)
Filed by Raynergy Tek Incorporation, Hsinchu (TW)
Filed on Aug. 15, 2022, as Appl. No. 17/819,792.
Claims priority of application No. 111117724 (TW), filed on May 11, 2022.
Prior Publication US 2023/0371293 A1, Nov. 16, 2023
Int. Cl. H10K 30/81 (2023.01); H10K 71/00 (2023.01)
CPC H10K 30/81 (2023.02) [H10K 71/621 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method of patterning a semiconductor layer, comprising:
forming a first electrode and a second electrode within a substrate;
forming a patterned polymer layer on the substrate, wherein the patterned polymer layer has a first portion located on a portion of the second electrode and a second portion located on an edge portion of the substrate;
depositing the semiconductor layer on the patterned polymer layer, the substrate, and the first electrode;
removing the first portion of the patterned polymer layer and the semiconductor layer located on the first portion to form a through-hole in the semiconductor layer to expose the portion of the second electrode; and
depositing a conductive block on the semiconductor layer and in the through-hole, wherein the conductive block in the through-hole completely fills the through-hole.