| CPC H10F 39/811 (2025.01) [G06N 3/045 (2023.01); G06N 3/048 (2023.01); G06N 3/065 (2023.01); H04N 25/70 (2023.01); H04N 25/77 (2023.01); H04N 25/79 (2023.01); H10F 39/809 (2025.01)] | 27 Claims |

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1. A semiconductor element comprising:
a first semiconductor layer including a first photoelectric converting unit for converting light into electrical charge, a second photoelectric converting unit for converting light into electrical charge and provided at a position in a first direction from the first photoelectric converting unit, a third photoelectric converting unit for converting light into electrical charge and provided at a position in a second direction intersecting the first direction from the first photoelectric converting unit;
a second semiconductor layer laminated on the first semiconductor layer and including a first converting unit for converting a signal on the basis of the electrical charge converted by the first photoelectric converting unit into a first signal having a digital value, a second converting unit for converting a signal on the basis of the electrical charge converted by the second photoelectric converting unit into a second signal having a digital value, and a third converting unit for converting a signal on the basis of the electrical charge converted by the third photoelectric converting unit into a third signal having a digital value;
a third semiconductor layer laminated on the first semiconductor layer and including a first multiplying circuit for performing a multiplication processing on the first signal, a second multiplying circuit for performing a multiplication processing on the second signal, and a third multiplying circuit for performing a multiplication processing on the third signal; and
a fourth semiconductor layer laminated on the first semiconductor layer and including an adding circuit for performing an adding processing by using at least two data among data acquired by the first multiplying circuit, data acquired by the second multiplying circuit, and data acquired by the third multiplying circuit.
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