US 12,396,279 B2
Solid-state image pickup apparatus and electronic equipment
Hiroaki Ammo, Kanagawa (JP); Hirokazu Ejiri, Kanagawa (JP); and Akiko Honjo, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Sep. 28, 2023, as Appl. No. 18/476,776.
Application 18/476,776 is a continuation of application No. 17/305,415, filed on Jul. 7, 2021, granted, now 11,804,500.
Application 17/305,415 is a continuation of application No. 16/496,619, granted, now 11,121,158, issued on Sep. 14, 2021, previously published as PCT/JP2018/010392, filed on Mar. 16, 2018.
Claims priority of application No. 2017-071599 (JP), filed on Mar. 31, 2017.
Prior Publication US 2024/0096915 A1, Mar. 21, 2024
Int. Cl. H10F 39/00 (2025.01); H10D 30/63 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 84/90 (2025.01); H10F 39/12 (2025.01); H10K 39/32 (2023.01)
CPC H10F 39/80377 (2025.01) [H10D 30/63 (2025.01); H10D 62/122 (2025.01); H10D 62/292 (2025.01); H10D 84/907 (2025.01); H10F 39/12 (2025.01); H10F 39/199 (2025.01); H10K 39/32 (2023.02); H01L 2924/13086 (2013.01); Y10S 977/938 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A light detecting device, comprising:
a photoelectric conversion region in a substrate, wherein the photoelectric conversion region is configured to generate a charge;
a first transistor that includes:
a first semiconductor area that extends in a vertical direction with respect to the substrate;
a gate around the first semiconductor area;
a first insulating film between the gate and the first semiconductor area; and
a second insulating film between the gate and the photoelectric conversion region;
a second transistor electrically connected to the first transistor, wherein
the first transistor is configured to transfer the generated charge to the second transistor,
the second transistor includes a second semiconductor area, and
the second semiconductor area is at a same level as of at least a part of the first semiconductor area; and
a wiring layer configured to electrically connect the first transistor to the second transistor, wherein the wiring layer is on the substrate.