| CPC H10D 86/0231 (2025.01) [H10D 86/451 (2025.01)] | 20 Claims |

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1. An array substrate, comprising:
a substrate;
a first insulating layer disposed on the substrate;
a second insulating layer disposed on the first insulating layer, a horizontal etching rate of the first insulating layer being greater than a horizontal etching rate of the second insulating layer; and
a third insulating layer disposed on the second insulating layer, a horizontal etching rate of the third insulating layer being greater than the horizontal etching rate of the second insulating layer;
wherein the array substrate is provided with a first region and a second region, and the array substrate comprises a first type of via holes and a second type of via holes, wherein the first type of via holes are disposed in the first region, the second type of via holes are disposed in the second region, the first type of via holes penetrate through the first insulating layer, the second insulating layer, and the third insulating layer, the second type of via holes penetrate through the third insulating layer, a hole depth of the first type of via holes is greater than that of the second type of via holes, and a pore diameter of the first type of via holes is greater than that of the second type of via holes.
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