| CPC H10D 86/0221 (2025.01) [H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 64/62 (2025.01); H10D 86/423 (2025.01); H10D 86/451 (2025.01); H10D 86/60 (2025.01)] | 7 Claims |

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1. An array substrate, comprising:
a base;
a primary gate electrode located on the base;
an active layer located on the primary gate electrode;
an etch stop layer located on the active layer;
a source electrode and a drain electrode located on the etch stop layer, and
a metal connection layer arranged on surfaces of the source electrode and the drain electrode away from the base, wherein the drain electrode is connected to a pixel through the metal connection layer;
wherein the source electrode and the drain electrode partly cover the etch stop layer, an area of the etch stop layer not covered by the source electrode and the drain electrode is configured to be an oxidized metal layer, and the oxidized metal layer corresponds to the active layer and the primary gate electrode;
wherein a thickness of a portion of the source electrode extending beyond the active layer is less than a total thickness of the source electrode, and a thickness of a portion of the drain electrode extending beyond the active layer is less than a total thickness of the drain electrode.
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