| CPC H10D 84/907 (2025.01) [G06F 30/392 (2020.01); G11C 5/06 (2013.01); G11C 11/412 (2013.01); H01L 23/528 (2013.01); H10D 89/10 (2025.01)] | 14 Claims |
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1. An integrated circuit comprising:
a first inverter including a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor, which are gated through a first metal line to which a first input voltage is configured to be applied, and configured to output a first inverted voltage by inverting the first input voltage, wherein a drain of the first NMOS transistor and a drain of the first PMOS transistor are routed through a first source/drain contact, a first metal line extends in a first direction, and the first source/drain contact extends in a second direction perpendicular to the first direction;
a first transmission gate including a second PMOS transistor gated through a second metal line to which a first active voltage is configured to be applied and a second NMOS transistor gated through a third metal line to which a second active voltage is configured to be applied, wherein a source of the second PMOS transistor and a drain of the second NMOS transistor are routed through the first source/drain contact, and a drain of the second PMOS transistor and a source of the second NMOS transistor are routed through a second source/drain contact; and
a first tri-state inverter including a third PMOS transistor gated through a fourth metal line to which the second active voltage is configured to be applied, a third NMOS transistor gated through a fifth metal line to which the first active voltage is configured to be applied, and a fourth PMOS transistor and a fourth NMOS transistor, which are gated through a sixth metal line to which a second input voltage is configured to be applied, and configured to invert the second input voltage, wherein a drain of the third PMOS transistor and a drain of the third NMOS transistor are routed through the second source/drain contact.
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