US 12,396,256 B2
Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit
Yi-Feng Chang, New Taipei (TW); Po-Lin Peng, Taoyuan (TW); and Jam-Wem Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jan. 16, 2024, as Appl. No. 18/413,869.
Application 16/525,275 is a division of application No. 15/691,725, filed on Aug. 30, 2017, granted, now 10,366,992, issued on Jul. 30, 2019.
Application 18/413,869 is a continuation of application No. 17/570,872, filed on Jan. 7, 2022, granted, now 11,908,859.
Application 17/570,872 is a continuation of application No. 16/525,275, filed on Jul. 29, 2019, granted, now 11,222,893, issued on Jan. 11, 2022.
Prior Publication US 2024/0153950 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/85 (2025.01); H10D 8/80 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 89/60 (2025.01)
CPC H10D 84/854 (2025.01) [H10D 8/80 (2025.01); H10D 62/115 (2025.01); H10D 62/371 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 89/713 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first region, a second region, a third region and a fourth region separated from each other;
a first metal contact coupling the first region to the second region;
a second metal contact coupling the third region to the fourth region, and isolated from the first metal contact; and
a first gate disposed between the first region and the second region, and disposed between the third region and the fourth region.