US 12,396,254 B2
Stacked 2D CMOS with inter metal layers
Kevin P. O'Brien, Portland, OR (US); Uygar E. Avci, Portland, OR (US); Scott B. Clendenning, Portland, OR (US); Chelsey Dorow, Portland, OR (US); Sudarat Lee, Hillsboro, OR (US); Kirby Maxey, Hillsboro, OR (US); Carl H. Naylor, Portland, OR (US); Tristan A. Tronic, Aloha, OR (US); Shriram Shivaraman, Hillsboro, OR (US); and Ashish Verma Penumatcha, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,225.
Prior Publication US 2023/0101760 A1, Mar. 30, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 23/48 (2006.01); H10B 10/00 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/85 (2025.01) [H01L 23/481 (2013.01); H10B 10/125 (2023.02); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/258 (2025.01); H10D 88/00 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor on a first level;
a second transistor on a second level above the first level;
an insulating layer between the first level and the second level; and
a via through the insulating layer, wherein the via electrically couples the first transistor to the second transistor, wherein each of the first transistor and the second transistor comprises:
a first channel;
a second channel over the first channel;
a gate structure between the first channel and the second channel;
a source contact on a first end of the first channel and the second channel; and
a drain contact on a second end of the first channel and the second channel.