| CPC H10D 84/83 (2025.01) [H01L 21/76895 (2013.01); H01L 23/485 (2013.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 84/0149 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)] | 20 Claims |

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1. A method comprising:
forming a first conductive structure as a single piece in contact with a first source/drain region of a first transistor and a second source/drain region of a second transistor, wherein there is no via between the first conductive structure and the first or second source/drain region, the first and second source/drain regions are at a common height from a first surface of a substrate, the first source/drain region of the first transistor is an output of a first electrical component of a first cell, and the second source/drain region of the second transistor is an input of a second electrical component of a second cell;
forming the first source/drain region on a side of a gate; and
forming the second source/drain region on the side of the gate.
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