US 12,396,248 B2
Semiconductor device fabrication methods and structures thereof
Chung-Wei Hsu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Mao-Lin Huang, Hsinchu (TW); Lung-Kun Chu, New Taipei (TW); Jia-Ni Yu, Hsinchu (TW); Kuan-Lun Cheng, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 24, 2024, as Appl. No. 18/673,960.
Application 18/673,960 is a continuation of application No. 18/069,052, filed on Dec. 20, 2022, granted, now 11,996,334.
Application 18/069,052 is a continuation of application No. 17/161,905, filed on Jan. 29, 2021, granted, now 11,600,533, issued on Mar. 7, 2023.
Claims priority of provisional application 63/080,289, filed on Sep. 18, 2020.
Prior Publication US 2024/0312845 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 30/6735 (2025.01); H10D 62/119 (2025.01); H10D 84/0172 (2025.01); H10D 84/0181 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate;
forming a dipole layer over the first channel layer and the second channel layer, wherein the dipole layer includes a p-dipole material;
forming a patterned hard mask covering the second channel layer and exposing the first channel layer;
removing the dipole layer from the first channel layer;
removing the patterned hard mask;
performing a thermal drive-in process;
forming an interfacial dielectric layer on the first channel layer and the dipole layer; and
forming a high-k dielectric layer on the interfacial dielectric layer.