US 12,396,245 B2
Semiconductor arrangement and method for making
Wei-Lun Chen, Taipei (TW); Chao-Hsien Huang, Tainan (TW); Li-Te Lin, Hsinchu (TW); and Pinyen Lin, Rochester, NY (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Dec. 6, 2021, as Appl. No. 17/542,802.
Application 17/542,802 is a continuation of application No. 16/589,353, filed on Oct. 1, 2019, granted, now 11,195,759.
Claims priority of provisional application 62/773,342, filed on Nov. 30, 2018.
Prior Publication US 2022/0093469 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/03 (2025.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/31116 (2013.01); H10D 30/024 (2025.01); H10D 84/0158 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor arrangement, comprising:
forming an opening in a dielectric layer, the opening exposing a fin concealed by the dielectric layer;
removing a first portion of the fin exposed though the opening;
forming a first protective layer along a sidewall of the dielectric layer defining the opening concurrently with removing the first portion of the fin;
removing a second portion of the fin exposed though the opening after forming the first protective layer; and
forming a second protective layer along the sidewall of the dielectric layer concurrently with removing the second portion of the fin.