| CPC H10D 64/667 (2025.01) [H01L 21/28026 (2013.01); H10D 62/151 (2025.01); H10D 64/411 (2025.01); H10D 64/691 (2025.01); H10D 84/0142 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate that includes a PMOSFET region and an NMOSFET region; and
a first transistor on the PMOSFET region and a second transistor on the NMOSFET region,
wherein:
the first transistor includes:
a first gate dielectric layer on the substrate;
a first lower metal pattern on the first gate dielectric layer;
a second lower metal pattern on the first lower metal pattern; and
a first intermediate pattern between the first lower metal pattern and the second lower metal pattern,
the second transistor includes:
a second gate dielectric layer on the substrate;
a third lower metal pattern on the second gate dielectric layer; and
a second intermediate pattern between the second gate dielectric layer and the third lower metal pattern,
the first intermediate pattern and the second intermediate pattern each include lanthanum,
the first lower metal pattern, the second lower metal pattern, and the third lower metal pattern each include a metal nitride,
a thickness of the first lower metal pattern is greater than a thickness of the third lower metal pattern;
a lanthanum concentration of the second lower metal pattern increases with decreasing distance from the first intermediate pattern, and
a lanthanum concentration of the first lower metal pattern increases with decreasing distance from the first intermediate pattern.
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