| CPC H10D 64/258 (2025.01) [H10D 30/797 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first active pattern spaced apart from a substrate and extending in a first direction;
a second active pattern spaced apart from the substrate and extending in the first direction, the first active pattern being provided between the second active pattern and the substrate;
a gate structure extending in a second direction on the substrate, the first active pattern and the second active pattern passing through the gate structure, and the second direction crossing the first direction;
a first source/drain area connected with the first active pattern and provided on a side of the gate structure;
a second source/drain area connected with the second active pattern and provided on the first source/drain area;
a first insulating structure provided between the substrate and the first source/drain area, wherein the first insulating structure is not provided between the substrate and the gate structure; and
a second insulating structure provided between the first source/drain area and the second source/drain area,
wherein the second insulating structure is offset from the first active pattern and the second active pattern along a third direction that is perpendicular to the first direction and the second direction.
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