US 12,396,234 B2
Method for forming semiconductor device structure with a cap layer
Ming-Lung Cheng, Kaohsiung (TW); Huang-Hsuan Lin, Hsinchu (TW); and Chih-Chieh Yeh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 15, 2022, as Appl. No. 17/721,668.
Prior Publication US 2023/0335600 A1, Oct. 19, 2023
Int. Cl. H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2025.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01)
CPC H10D 64/01 (2025.01) [H01L 21/0259 (2013.01); H01L 21/28088 (2013.01); H01L 21/32133 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/679 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device structure, comprising:
forming nanostructures over a substrate;
forming spacers over the nanostructures;
forming a work function layer surrounding the nanostructures;
forming a first metal layer over the work function layer and sidewalls of the spacers;
forming a second metal layer surrounded by the first metal layer;
etching the first metal layer over opposite sides of the second metal layer; and
forming a cap layer over a top surface and a sidewall of the second metal layer, wherein a bottom surface of the cap layer is lower a bottom surface of the second metal layer.