US 12,396,233 B2
Semiconductor device having backside via and method of fabricating thereof
Lin-Yu Huang, Hsinchu (TW); Li-Zhen Yu, New Taipei (TW); Chia-Hao Chang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/649,312.
Application 17/649,312 is a continuation of application No. 16/948,712, filed on Sep. 29, 2020, granted, now 11,239,325.
Claims priority of provisional application 63/016,686, filed on Apr. 28, 2020.
Prior Publication US 2022/0157949 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/01 (2025.01) [H10D 30/0245 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 64/513 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a gate structure interposing two source/drain (S/D) features;
a bottom dielectric layer below the gate structure and at least one of the two S/D features;
a contact extending from below a first S/D feature of the two S/D features, wherein the contact has a first width at a terminal end and a second width measured in the same direction as the first width and adjacent the bottom dielectric layer, wherein the first width is less than the second width; and
a metal line physically connected to the terminal end of the contact.