US 12,396,229 B2
Semiconductor device
Yi-Tse Hung, Hsinchu (TW); Ang-Sheng Chou, Hsinchu (TW); Hung-Li Chiang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); and Chao-Ching Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 4, 2024, as Appl. No. 18/764,317.
Application 18/352,249 is a division of application No. 17/351,244, filed on Jun. 18, 2021, granted, now 11,749,718, issued on Sep. 5, 2023.
Application 18/764,317 is a continuation of application No. 18/352,249, filed on Jul. 14, 2023, granted, now 12,062,696.
Claims priority of provisional application 63/156,932, filed on Mar. 5, 2021.
Prior Publication US 2024/0363688 A1, Oct. 31, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 23/36 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01)
CPC H10D 62/235 (2025.01) [H01L 23/36 (2013.01); H10D 30/021 (2025.01); H10D 30/60 (2025.01); H10D 62/102 (2025.01); H10D 62/119 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first heat transfer layer disposed over a semiconductor substrate;
a channel material layer, disposed on the first heat transfer layer and in contact with the first heat transfer layer, the channel material layer includes a semiconducting two-dimensional (2D) material, and the first heat transfer layer includes an insulating 2D material, and the first heat transfer layer has a thermal conductivity higher than that of the channel material layer;
a gate structure disposed above the channel material layer; and
source and drain terminals, located at two opposite sides of the gate structure and in contact with the channel material layer.