US 12,396,224 B2
Integrated circuit device
Minhee Choi, Suwon-si (KR); Seojin Jeong, Suwon-si (KR); Seokhoon Kim, Suwon-si (KR); Jungtaek Kim, Suwon-si (KR); Pankwi Park, Suwon-si (KR); Moonseung Yang, Suwon-si (KR); and Ryong Ha, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 4, 2023, as Appl. No. 18/527,453.
Application 18/527,453 is a continuation of application No. 17/467,944, filed on Sep. 7, 2021, granted, now 11,888,026.
Claims priority of application No. 10-2020-0173677 (KR), filed on Dec. 11, 2020.
Prior Publication US 2024/0096945 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/118 (2025.01) [H10D 30/6713 (2025.01); H10D 64/021 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a fin-type active region extending in a first horizontal direction on a substrate; and
forming a source/drain region on the fin-type active region by sequentially forming a lower main body layer and an upper main body layer on the fin-type active region,
wherein a top surface of the lower main body layer includes a non-linear portion and a lower facet declining toward the substrate as it extends in a direction to a center of the source/drain region,
wherein the upper main body layer includes a bottom surface contacting the non-linear portion and the lower facet of the top surface of the lower main body layer, and a top surface having an upper facet, and
wherein with respect to a vertical cross section, the lower facet extends along a first line, and the upper facet extends along a second line intersecting the first line.