US 12,396,222 B2
RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same
Cheng-Ta Wu, Hsinchu (TW); and Chiu Hua Chen, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 11, 2024, as Appl. No. 18/632,712.
Application 18/632,712 is a division of application No. 17/838,359, filed on Jun. 13, 2022, granted, now 11,984,477.
Application 17/838,359 is a division of application No. 16/885,341, filed on May 28, 2020, granted, now 11,362,176, issued on Jun. 14, 2022.
Prior Publication US 2024/0274659 A1, Aug. 15, 2024
Int. Cl. H01L 21/28 (2025.01); H01L 21/322 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/83 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 86/00 (2025.01); H10D 84/90 (2025.01)
CPC H10D 62/116 (2025.01) [H01L 21/28035 (2013.01); H01L 21/3226 (2013.01); H01L 21/76202 (2013.01); H10D 30/0413 (2025.01); H10D 30/6739 (2025.01); H10D 30/6758 (2025.01); H10D 30/69 (2025.01); H10D 62/83 (2025.01); H10D 64/66 (2025.01); H10D 64/661 (2025.01); H10D 64/671 (2025.01); H10D 84/0112 (2025.01); H10D 84/0165 (2025.01); H10D 84/038 (2025.01); H10D 86/201 (2025.01); H01J 2237/0437 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1517 (2013.01); H10D 84/957 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
depositing a polysilicon material layer on a top surface of a handle substrate;
converting the polysilicon material layer into a nitrogen-doped polysilicon layer;
thermally oxidizing a top portion of the nitrogen-doped polysilicon layer into a thermal oxide layer;
forming a semiconductor device in a remaining portion of the nitrogen-doped polysilicon layer and the thermal oxide layer; and
attaching a semiconductor material layer on a top surface of the thermal oxide layer and a top surface of the semiconductor device.