US 12,396,215 B2
Semiconductor device and electronic device
Shunpei Yamazaki, Tokyo (JP); Hajime Kimura, Kanagawa (JP); and Hitoshi Kunitake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Dec. 6, 2023, as Appl. No. 18/530,797.
Application 18/530,797 is a continuation of application No. 17/712,224, filed on Apr. 4, 2022, granted, now 11,843,059.
Application 17/712,224 is a continuation of application No. 17/011,385, filed on Sep. 3, 2020, granted, now 11,335,812, issued on May 17, 2022.
Claims priority of application No. 2019-199005 (JP), filed on Oct. 31, 2019; application No. 2019-203738 (JP), filed on Nov. 11, 2019; application No. 2019-208041 (JP), filed on Nov. 18, 2019; application No. 2019-216249 (JP), filed on Nov. 29, 2019; and application No. 2019-230250 (JP), filed on Dec. 20, 2019.
Prior Publication US 2024/0105855 A1, Mar. 28, 2024
Int. Cl. H01L 27/10 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10B 41/27 (2023.01); H10B 43/30 (2023.01); H10D 30/67 (2025.01); H10D 84/00 (2025.01)
CPC H10D 30/6755 (2025.01) [H10B 12/30 (2023.02); H10B 41/27 (2023.02); H10B 43/30 (2023.02); H10D 84/00 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit, the first circuit comprising:
a plurality of planar transistors arranged adjacent to each other; and
a memory cell over the first circuit, the memory cell comprising:
a first transistor;
a second transistor; and
a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor and a gate of the second transistor,
wherein the plurality of planar transistors is formed on a silicon substrate,
wherein a first semiconductor extends in a direction perpendicular to the silicon substrate,
wherein a second semiconductor extends in the direction perpendicular to the silicon substrate,
wherein the first semiconductor comprises a channel formation region of the first transistor, and
wherein the second semiconductor comprises a channel formation region of the second transistor.