| CPC H10D 30/6748 (2025.01) [H10D 64/511 (2025.01)] | 18 Claims |
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1. A semiconductor device, comprising:
a logic cell on a substrate, the logic cell including a PMOSFET region and an NMOSFET region; and
a first metal layer on the logic cell,
wherein the first metal layer includes,
a first power line and a second power line that extend parallel to each other along a first direction, and
a first lower line, a second lower line, and a third lower line respectively on a first wiring track, a second wiring track, and a third wiring track that are defined between the first power line and the second power line,
wherein the first wiring track, the second wiring track, and the third wiring track extend parallel to each other along the first direction,
the first lower line includes a first line and a second line that are spaced apart from each other in the first direction at a first distance,
the third lower line includes a third line and a fourth line that are spaced apart from each other in the first direction at a second distance different from the first distance,
the first line has a first convex end that faces the second line and a third convex end that is opposite to the first end, and a convex curvature at the third end is different from a convex curvature at the first end,
the third line has a second end that faces the fourth line, and
a curvature at the first end is the same as a curvature at the second end.
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