| CPC H10D 30/6713 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01)] | 20 Claims |
|
1. A method for forming a semiconductor device, the method comprising:
forming a fin structure including two or more first semiconductor layers alternately stacked with two or more second semiconductor layers;
forming a sacrificial gate structure over the fin structure;
forming an inner sidewall spacer over a sidewall of the sacrificial gate structure, wherein the inner sidewall spacer has a side surface facing away from the sacrificial gate structure;
etching back the fin structure along the side surface of the inner sidewall spacer;
forming inner spacers by partially removing two or more second semiconductor layers and filling a dielectric material therein;
epitaxially growing a source/drain feature from the two or more first semiconductor layers, wherein the source/drain feature has a side when viewed from a first direction and a facet surface when viewed from a second direction substantially perpendicular to the first direction, the side and the facet surface share an edge, and the side of the source/drain feature is in contact the inner spacers and a portion of the side surface of the inner sidewall spacer;
forming an outer sidewall spacer over the side surface of the inner sidewall spacer, wherein the outer sidewall spacer is in contact with the facet surface of the source/drain feature;
depositing a contact etch stop layer (CESL) over the outer sidewall spacer and the source/drain feature; and
depositing an interlayer dielectric (ILD) layer over the CESL.
|