US 12,396,209 B2
Semiconductor device and method
Shao-Yang Ma, Tainan (TW); Cheng-Yen Wen, Taichung (TW); Li-Li Su, ChuBei (TW); Chii-Horng Li, Zhubei (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 12, 2022, as Appl. No. 17/663,165.
Prior Publication US 2023/0369502 A1, Nov. 16, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/6713 (2025.01) [H01L 21/02576 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a stack of nanostructures over a substrate;
forming a recess through the stack of nanostructures;
depositing a first semiconductor layer in the recess, wherein the first semiconductor layer is amorphous;
annealing the first semiconductor layer, wherein the annealing crystallizes a first portion of the first semiconductor layer; and
depositing a second semiconductor layer over the first portion of the first semiconductor layer.