| CPC H10D 30/63 (2025.01) [H01L 23/5226 (2013.01); H10D 64/01 (2025.01); H10D 64/252 (2025.01); H10D 64/513 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
a word line structure positioned in the substrate;
a plurality of impurity regions positioned in the substrate and adjacent to the word line structure;
a plurality of bottom shallow contacts positioned on the word line structure;
a first interconnect layer positioned on the plurality of bottom shallow contacts;
a plurality of top shallow contacts positioned on the first interconnect layer;
a plurality of deep contacts positioned on the plurality of impurity regions; and
a second interconnect layer positioned on the plurality of top shallow contacts, and a plurality of third interconnect layers positioned on the plurality of deep contacts;
wherein the width of the first interconnect layer and a width of the second interconnect layer are different.
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