US 12,396,205 B2
Semiconductor device having fins and method of fabricating the same
Shu-Hao Kuo, Tainan (TW); Jung-Hao Chang, Taichung (TW); Chao-Hsien Huang, Tainan (TW); Li-Te Lin, Hsinchu (TW); and Kuo-Cheng Ching, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 21, 2024, as Appl. No. 18/670,123.
Application 18/670,123 is a division of application No. 18/070,285, filed on Nov. 28, 2022, granted, now 12,027,625.
Application 16/880,864 is a division of application No. 16/141,509, filed on Sep. 25, 2018, granted, now 10,680,109, issued on Jun. 9, 2020.
Application 18/070,285 is a continuation of application No. 16/880,864, filed on May 21, 2020, granted, now 11,515,423, issued on Nov. 29, 2022.
Claims priority of provisional application 62/565,020, filed on Sep. 28, 2017.
Prior Publication US 2024/0313116 A1, Sep. 19, 2024
Int. Cl. H10D 30/62 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H10D 30/6212 (2025.01) [H01L 21/30604 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/76229 (2013.01); H10D 30/024 (2025.01); H10D 30/0241 (2025.01); H10D 30/6219 (2025.01); H10D 62/115 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 86/011 (2025.01); H10D 86/215 (2025.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first fin structure comprising:
a first semiconductive bottom portion; and
a first semiconductive top portion over the first semiconductive bottom portion, wherein the first semiconductive bottom portion is wider than the first semiconductive top portion;
a second fin structure comprising:
a second semiconductive bottom portion;
a dielectric middle portion over the second semiconductive bottom portion, wherein a top surface of the first semiconductive bottom portion of the first fin structure is lower than a top surface of the second semiconductive bottom portion of the second fin structure; and
a second semiconductive top portion over the dielectric middle portion; and
an isolation structure extending from the first fin structure to the second fin structure, wherein the isolation structure that extends from the first fin structure to the second fin structure is spaced apart from the dielectric middle portion of the second fin structure.